CD4015 consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one CD4015 package, or to more than 8 stages using additional CD4015’s is possible. The CD4015-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). Features:- Medium speed operation…12 MHz (typ.) clock rate at VDD – VSS = 10 V Fully static operation 8 master-slave flip-flops plus input and output buffering 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Standardized, symmetrical output characteristics Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
